1. Field of the Invention
This invention relates to an output buffer circuit of a semiconductor integrated circuit device, and particularly to an output circuit that makes the gradient of a rise/fall waveform of an output gentler.
2. Description of the Related Art
In a semiconductor integrated circuit device, if a rise/fall output waveform at the time of switching is steep, noise easily occurs in the power-supply potential and GND. Therefore, as a method for reducing the switching noise, it is conventionally effective to increase the rise/fall time (to make the gradient gentler).
As a conventional circuit for making the rise/fall gradient of an output waveform gentler, a slew-rate output circuit of a CMOS transistor as shown in FIG. 1 is used. The main features of its circuit structure will now be described. An input A is connected to the gates of a PMOS transistor P22, an NMOS transistor N22, a PMOS transistor P23 and an NMOS transistor N23 constituting initial-stage inverters C22 and C23. Transfer gates T22 and T23 are connected to the initial-stage inverters C22 and C23, respectively. The drain of the PMOS transistor P22 is connected to the gate of a PMOS transistor P24 constituting a next-stage inverter C24. The drain of the NMOS transistor N23 is connected to the gate of an NMOS transistor N24 of the next-stage inverter.
An output of the next-stage inverter NC24 is connected to the gates of the transfer gates T22 and T23. The drains of the transfer gates T22 and T23 are connected to the gates of a PMOS transistor P21 and an NMOS transistor N21 constituting an output transistor, respectively. An output Y is taken out from the drain of a CMOS output transistor C21 connected to a first power-supply potential Vc and a second power-supply potential Vs (GND).
In the operation of this circuit, first, when the input A is switched from 0 (L) to a power-supply voltage (H), the NMOS transistor N22 is turned into ON-state. Influenced by ON-state resistance of the transfer gate T22, the gate potentials of the PMOS transistors P21 and P24 are gradually switched to L, and after a while, the PMOS transistors P21 and P24 are turned into ON-state. When also the NMOS transistor of the transfer gate T22 is turned into ON-state, the fall in gate potential of the PMOS transistors P21 and P24 becomes much gentler. As a result, the output Y has a gentle rise waveform.
When the input A is switched from the power-supply voltage (H) to 0 (L), the PMOS transistor P23 is turned into ON-state. Influenced by ON-state resistance of the transfer gate T23, the gate potentials of the NMOS transistors N21 and N24 are gradually switched to H, and after a while, the NMOS transistors N21 and N24 are turned into ON-state. Since also the PMOS transistor of the transfer gate T23 is turned into ON-state, the rise in gate potential of the NMOS transistors N21 and N24 becomes much gentler. As a result, the output Y has a gentle fall waveform.
Other than the above-described technique, JP-A-5-218847, JP-A-9-148909, JP-A-10-290154, and Japanese Patent No.3,014,164 disclose output circuits for controlling the slew rate in order to prevent the switching noise.
However, in the above-described circuit for controlling the rise/fall time of an output waveform (to make the waveform gradient gentler) using the transfer gates, in order to increase ON-state resistance and make the rise/fall in gate potential of the output transistor gentler, a large number of constituent transistors must be used in the transfer gates for controlling the output transistor. Moreover, even a dimensional change of the transistors is not enough for making the waveform gradient gentler, and a problem arises that only the delay of an output signal increases while the waveform does not become gentler.